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    <subfield code="a">3rd ed.</subfield>
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    <subfield code="a">Includes bibliographical references and index.</subfield>
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    <subfield code="g">1.</subfield>
    <subfield code="t">Binary Systems -- </subfield>
    <subfield code="g">1-1.</subfield>
    <subfield code="t">Digital Computers and Digital Systems -- </subfield>
    <subfield code="g">1-2.</subfield>
    <subfield code="t">Binary Numbers -- </subfield>
    <subfield code="g">1-3.</subfield>
    <subfield code="t">Number Base Conversions -- </subfield>
    <subfield code="g">1-4.</subfield>
    <subfield code="t">Octal and Hexadecimal Numbers -- </subfield>
    <subfield code="g">1-5.</subfield>
    <subfield code="t">Complements -- </subfield>
    <subfield code="g">1-6.</subfield>
    <subfield code="t">Signed Binary Numbers -- </subfield>
    <subfield code="g">1-7.</subfield>
    <subfield code="t">Binary Codes -- </subfield>
    <subfield code="g">1-8.</subfield>
    <subfield code="t">Binary Storage and Registers -- </subfield>
    <subfield code="g">1-9.</subfield>
    <subfield code="t">Binary Logic -- </subfield>
    <subfield code="g">2.</subfield>
    <subfield code="t">Boolean Algebra and Logic Gates -- </subfield>
    <subfield code="g">2-1.</subfield>
    <subfield code="t">Basic Definitions -- </subfield>
    <subfield code="g">2-2.</subfield>
    <subfield code="t">Axiomatic Definition of Boolean Algebra -- </subfield>
    <subfield code="g">2-3.</subfield>
    <subfield code="t">Basic Theorems and Properties of Boolean Algebra -- </subfield>
    <subfield code="g">2-4.</subfield>
    <subfield code="t">Boolean Functions -- </subfield>
    <subfield code="g">2-5.</subfield>
    <subfield code="t">Canonical and Standard Forms -- </subfield>
    <subfield code="g">2-6.</subfield>
    <subfield code="t">Other Logic Operations -- </subfield>
    <subfield code="g">2-7.</subfield>
    <subfield code="t">Digital Logic Gates -- </subfield>
    <subfield code="g">2-8.</subfield>
    <subfield code="t">Integrated Circuits -- </subfield>
    <subfield code="g">3.</subfield>
    <subfield code="t">Simplification of Boolean Functions -- </subfield>
    <subfield code="g">3-1.</subfield>
    <subfield code="t">The Map Method -- </subfield>
    <subfield code="g">3-2.</subfield>
    <subfield code="t">Two- and Three-Variable Maps -- </subfield>
    <subfield code="g">3-3.</subfield>
    <subfield code="t">Four-Variable Map -- </subfield>
    <subfield code="g">3-4.</subfield>
    <subfield code="t">Five-Variable Map -- </subfield>
    <subfield code="g">3-5.</subfield>
    <subfield code="t">Product of Sums Simplification -- </subfield>
    <subfield code="g">3-6.</subfield>
    <subfield code="t">NAND and NOR Implementation -- </subfield>
    <subfield code="g">3-7.</subfield>
    <subfield code="t">Other Two-Level Implementations -- </subfield>
    <subfield code="g">3-8.</subfield>
    <subfield code="t">Don't-Care Conditions -- </subfield>
    <subfield code="g">3-9.</subfield>
    <subfield code="t">The Tabulation Method -- </subfield>
    <subfield code="g">3-10.</subfield>
    <subfield code="t">Determination of Prime Implicants -- </subfield>
    <subfield code="g">3-11.</subfield>
    <subfield code="t">Selection of Prime Implicants -- </subfield>
    <subfield code="g">3-12.</subfield>
    <subfield code="t">Concluding Remarks -- </subfield>
    <subfield code="g">4.</subfield>
    <subfield code="t">Combinational Logic -- </subfield>
    <subfield code="g">4-1.</subfield>
    <subfield code="t">Introduction -- </subfield>
    <subfield code="g">4-2.</subfield>
    <subfield code="t">Design Procedure -- </subfield>
    <subfield code="g">4-3.</subfield>
    <subfield code="t">Adders -- </subfield>
    <subfield code="g">4-4.</subfield>
    <subfield code="t">Subtractors -- </subfield>
    <subfield code="g">4-5.</subfield>
    <subfield code="t">Code Conversion -- </subfield>
    <subfield code="g">4-6.</subfield>
    <subfield code="t">Analysis Procedure -- </subfield>
    <subfield code="g">4-7.</subfield>
    <subfield code="t">Multilevel NAND Circuits -- </subfield>
    <subfield code="g">4-8.</subfield>
    <subfield code="t">Multilevel NOR Circuits -- </subfield>
    <subfield code="g">4-9.</subfield>
    <subfield code="t">Exclusive-OR Functions -- </subfield>
    <subfield code="g">5.</subfield>
    <subfield code="t">MSI and PLD Components -- </subfield>
    <subfield code="g">5-1.</subfield>
    <subfield code="t">Introduction -- </subfield>
    <subfield code="g">5-2.</subfield>
    <subfield code="t">Binary Adder and Subtractor -- </subfield>
    <subfield code="g">5-3.</subfield>
    <subfield code="t">Decimal Adder -- </subfield>
    <subfield code="g">5-4.</subfield>
    <subfield code="t">Magnitude Comparator -- </subfield>
    <subfield code="g">5-5.</subfield>
    <subfield code="t">Decoders and Encoders -- </subfield>
    <subfield code="g">5-6.</subfield>
    <subfield code="t">Multiplexers -- </subfield>
    <subfield code="g">5-7.</subfield>
    <subfield code="t">Read-Only Memory (ROM) -- </subfield>
    <subfield code="g">5-8.</subfield>
    <subfield code="t">Programmable Logic Array (PLA) -- </subfield>
    <subfield code="g">5-9.</subfield>
    <subfield code="t">Programmable Array Logic (PAL) -- </subfield>
    <subfield code="g">6.</subfield>
    <subfield code="t">Synchronous Sequential Logic -- </subfield>
    <subfield code="g">6-1.</subfield>
    <subfield code="t">Introduction -- </subfield>
    <subfield code="g">6-2.</subfield>
    <subfield code="t">Flip-Flops -- </subfield>
    <subfield code="g">6-3.</subfield>
    <subfield code="t">Triggering of Flip-Flops -- </subfield>
    <subfield code="g">6-4.</subfield>
    <subfield code="t">Analysis of Clocked Sequential Circuits -- </subfield>
    <subfield code="g">6-5.</subfield>
    <subfield code="t">State Reduction and Assignment -- </subfield>
    <subfield code="g">6-6.</subfield>
    <subfield code="t">Flip-Flop Excitation Tables -- </subfield>
    <subfield code="g">6-7.</subfield>
    <subfield code="t">Design Procedure -- </subfield>
    <subfield code="g">6-8.</subfield>
    <subfield code="t">Design of Counters -- </subfield>
    <subfield code="g">7.</subfield>
    <subfield code="t">Registers, Counters, and the Memory Unit -- </subfield>
    <subfield code="g">7-1.</subfield>
    <subfield code="t">Introduction -- </subfield>
    <subfield code="g">7-2.</subfield>
    <subfield code="t">Registers -- </subfield>
    <subfield code="g">7-3.</subfield>
    <subfield code="t">Shift Registers -- </subfield>
    <subfield code="g">7-4.</subfield>
    <subfield code="t">Ripple Counters -- </subfield>
    <subfield code="g">7-5.</subfield>
    <subfield code="t">Synchronous Counters -- </subfield>
    <subfield code="g">7-6.</subfield>
    <subfield code="t">Timing Sequences -- </subfield>
    <subfield code="g">7-7.</subfield>
    <subfield code="t">Random-Access Memory (RAM) -- </subfield>
    <subfield code="g">7-8.</subfield>
    <subfield code="t">Memory Decoding -- </subfield>
    <subfield code="g">7-9.</subfield>
    <subfield code="t">Error-Correcting Codes -- </subfield>
    <subfield code="g">8.</subfield>
    <subfield code="t">Algorithmic State Machines (ASM) -- </subfield>
    <subfield code="g">8-1.</subfield>
    <subfield code="t">Introduction -- </subfield>
    <subfield code="g">8-2.</subfield>
    <subfield code="t">ASM Chart -- </subfield>
    <subfield code="g">8-3.</subfield>
    <subfield code="t">Timing Considerations -- </subfield>
    <subfield code="g">8-4.</subfield>
    <subfield code="t">Control Implementation -- </subfield>
    <subfield code="g">8-5.</subfield>
    <subfield code="t">Design with Multiplexers -- </subfield>
    <subfield code="g">8-6.</subfield>
    <subfield code="t">PLA Control -- </subfield>
    <subfield code="g">9.</subfield>
    <subfield code="t">Asynchronous Sequential Logic -- </subfield>
    <subfield code="g">9-1.</subfield>
    <subfield code="t">Introduction -- </subfield>
    <subfield code="g">9-2.</subfield>
    <subfield code="t">Analysis Procedure -- </subfield>
    <subfield code="g">9-3.</subfield>
    <subfield code="t">Circuits with Latches -- </subfield>
    <subfield code="g">9-4.</subfield>
    <subfield code="t">Design Procedure -- </subfield>
    <subfield code="g">9-5.</subfield>
    <subfield code="t">Reduction of State and Flow Tables -- </subfield>
    <subfield code="g">9-6.</subfield>
    <subfield code="t">Race-Free State Assignment -- </subfield>
    <subfield code="g">9-7.</subfield>
    <subfield code="t">Hazards -- </subfield>
    <subfield code="g">9-8.</subfield>
    <subfield code="t">Design Example -- </subfield>
    <subfield code="g">10.</subfield>
    <subfield code="t">Digital Integrated Circuits -- </subfield>
    <subfield code="g">10-1.</subfield>
    <subfield code="t">Introduction -- </subfield>
    <subfield code="g">10-2.</subfield>
    <subfield code="t">Special Characteristics -- </subfield>
    <subfield code="g">10-3.</subfield>
    <subfield code="t">Bipolar-Transistor Characteristics -- </subfield>
    <subfield code="g">10-4.</subfield>
    <subfield code="t">RTL and DTL Circuits -- </subfield>
    <subfield code="g">10-5.</subfield>
    <subfield code="t">Transistor-Transistor Logic (TTL) -- </subfield>
    <subfield code="g">10-6.</subfield>
    <subfield code="t">Emmitter-Coupled Logic (ECL) -- </subfield>
    <subfield code="g">10-7.</subfield>
    <subfield code="t">Metal-Oxide Semiconductor (MOS) -- </subfield>
    <subfield code="g">10-8.</subfield>
    <subfield code="t">Complementary MOS (CMOS) -- </subfield>
    <subfield code="g">10-9.</subfield>
    <subfield code="t">CMOS Transmission Gate Circuits -- </subfield>
    <subfield code="g">11.</subfield>
    <subfield code="t">Laboratory Experiments -- </subfield>
    <subfield code="g">11-0.</subfield>
    <subfield code="t">Introduction to Experiments -- </subfield>
    <subfield code="g">11-1.</subfield>
    <subfield code="t">Binary and Decimal Numbers -- </subfield>
    <subfield code="g">11-2.</subfield>
    <subfield code="t">Digital Logic Gates -- </subfield>
    <subfield code="g">11-3.</subfield>
    <subfield code="t">Simplification of Boolean Functions -- </subfield>
    <subfield code="g">11-4.</subfield>
    <subfield code="t">Combinational Circuits -- </subfield>
    <subfield code="g">11-5.</subfield>
    <subfield code="t">Code Converters -- </subfield>
    <subfield code="g">11-6.</subfield>
    <subfield code="t">Design with Multiplexers -- </subfield>
    <subfield code="g">11-7.</subfield>
    <subfield code="t">Adders and Subtractors -- </subfield>
    <subfield code="g">11-8.</subfield>
    <subfield code="t">Flip-Flops -- </subfield>
    <subfield code="g">11-9.</subfield>
    <subfield code="t">Sequential Circuits -- </subfield>
    <subfield code="g">11-10.</subfield>
    <subfield code="t">Counters -- </subfield>
    <subfield code="g">11-11.</subfield>
    <subfield code="t">Shift Registers -- </subfield>
    <subfield code="g">11-12.</subfield>
    <subfield code="t">Serial Addition -- </subfield>
    <subfield code="g">11-13.</subfield>
    <subfield code="t">Memory Unit -- </subfield>
    <subfield code="g">11-14.</subfield>
    <subfield code="t">Lamp Handball -- </subfield>
    <subfield code="g">11-15.</subfield>
    <subfield code="t">Clock-Pulse Generator -- </subfield>
    <subfield code="g">11-16.</subfield>
    <subfield code="t">Parallel Adder -- </subfield>
    <subfield code="g">11-17.</subfield>
    <subfield code="t">Binary Multiplier -- </subfield>
    <subfield code="g">11-18.</subfield>
    <subfield code="t">Asynchronous Sequential Circuits -- </subfield>
    <subfield code="g">12.</subfield>
    <subfield code="t">Standard Graphic Symbols -- </subfield>
    <subfield code="g">12-1.</subfield>
    <subfield code="t">Rectangular-Shape Symbols -- </subfield>
    <subfield code="g">12-2.</subfield>
    <subfield code="t">Qualifying Symbols -- </subfield>
    <subfield code="g">12-3.</subfield>
    <subfield code="t">Dependency Notation -- </subfield>
    <subfield code="g">12-4.</subfield>
    <subfield code="t">Symbols for Combinational Elements -- </subfield>
    <subfield code="g">12-5.</subfield>
    <subfield code="t">Symbols for Flip-Flops -- </subfield>
    <subfield code="g">12-6.</subfield>
    <subfield code="t">Symbols for Registers -- </subfield>
    <subfield code="g">12-7.</subfield>
    <subfield code="t">Symbols for Counters -- </subfield>
    <subfield code="g">12-8.</subfield>
    <subfield code="t">Symbol for RAM -- </subfield>
    <subfield code="g">Appendix.</subfield>
    <subfield code="t">Answers to Selected Problems.</subfield>
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