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Digital integrated circuits : a design perspective / Jan M. Rabaey.

By: Material type: TextTextSeries: Prentice Hall electronics and VLSI seriesPublication details: Upper Saddle River, N.J. : Prentice Hall, c1996.Description: xviii, 702 p., [8] p. of plates : ill. (some col.) ; 25 cmISBN:
  • 0131786091
Subject(s): DDC classification:
  • 621.39/5 20
LOC classification:
  • TK7874.65 .R33 1996
Contents:
Ch. 1. Introduction -- Ch. 2. The Devices -- Appendix A: Layout Design Rules -- Appendix B: Small-Signal Models -- Ch. 3. The Inverter -- Ch. 4. Designing Combinational Logic Gates in CMOS -- Appendix C: Layout Techniques for Complex Gates -- Ch. 5. Very High Performance Digital Circuits -- Appendix D: The Schottky-Barrier Diode -- Ch. 6. Designing Sequential Logic Circuits -- Ch. 7. Designing Arithmetic Building Blocks -- Appendix E: From Datapath Schematics to Layout -- Ch. 8. Coping with Interconnect -- Ch. 9. Timing Issues in Digital Circuits -- Ch. 10. Designing Memory and Array Structures -- Ch. 11. Design Methodologies.
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Holdings
Item type Current library Call number Copy number Status Date due Barcode Item holds
Loan - Normal on open shelf Loan - Normal on open shelf UOE Main Library Open shelf TK7868.D4.R33 1996 (Browse shelf(Opens below)) 2019205 Available 20139205
Total holds: 0

Includes bibliographical references and index.

Ch. 1. Introduction -- Ch. 2. The Devices -- Appendix A: Layout Design Rules -- Appendix B: Small-Signal Models -- Ch. 3. The Inverter -- Ch. 4. Designing Combinational Logic Gates in CMOS -- Appendix C: Layout Techniques for Complex Gates -- Ch. 5. Very High Performance Digital Circuits -- Appendix D: The Schottky-Barrier Diode -- Ch. 6. Designing Sequential Logic Circuits -- Ch. 7. Designing Arithmetic Building Blocks -- Appendix E: From Datapath Schematics to Layout -- Ch. 8. Coping with Interconnect -- Ch. 9. Timing Issues in Digital Circuits -- Ch. 10. Designing Memory and Array Structures -- Ch. 11. Design Methodologies.

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